The present invention concerns a solid-state imaging apparatus such as a CMOS sensor or a CCD sensor for obtaining image information and positional information by using a photoelectric conversion effect and it particularly relates to a solid-state imaging apparatus intending to reduce optical crosstalk by improvement in a well structure.
Solid-state imaging apparatus represented by CMOS sensors and CCD sensors have been applied generally to video cameras, digital still cameras, etc. In the solid-state imaging apparatus using the CMOS sensor, a CMOS transistor is used as a switching device for selecting photoelectric conversion devices (photodiode PD) or a switching device for reading signal charges. Further, an MOS transistor or CMOS transistor is used for peripheral circuits such as a control circuit and a signal processing circuit, and the apparatus have an advantage capable of manufacturing photoelectric conversion device PD, and the switching device, the peripheral circuits, etc. on one identical chip in a series of procedures.
In the solid-state imaging apparatus, a plurality of pixels each provided with a photoelectric conversion device are arranged on a semiconductor substrate. Light incident on each of the pixels is photoelectrically converted by the photodiode to form and collect electric charges, the charges are transferred to a floating diffusion (FD) part, and the potential fluctuation in the FD part is detected by an MOS transistor and converted into electric signals, which are amplified and outputted as video signals.
The photoelectric conversion device PD is formed of a PN junction and, generally electric charges are collected by utilizing an electric field in a depletion layer generated by application of a voltage. In a solid-state imaging apparatus for an incident light in a visible light region (380 nm to 830 nm), most of incident light is absorbed in a depth of about 5 μm from the Si surface to generate photocharges in the charge collection system. Accordingly, for collecting photocharges generated at high efficiency, it is necessary to ensure a sufficient width of the depletion layer, for example, of about 5 μm. Therefore, it is necessary to increase the depth of the PN junction and increase the voltage. Japanese Unexamined Patent Application Publication No. 2004-031878 discloses an example of such technique.